As demands in the semiconductor industry call for further miniaturization and performance enhancement of electronic systems, billions of transistors are now interconnected with tens of kilometers of wires that packed into an area of square centimeters. The complexity of the multi metallization levels of back-end-of-line (BEOL) brings challenges such as the need to decrease the resistive-capacitive (RC) delay, dynamic power consumption, cross-talk noise and reliability issues. Low-k dielectrics, such as carbon-doped silicon oxide (SiCOH), have been proposed as BEOL dielectrics. This includes applications which embed non-volatile memories (NVMs), such as magnetoresistive memories, in low-k BEOL dielectrics.
However, current processes for chemical mechanical planarization (CMP) of low-k dielectrics have challenges. For example, current low-k applications have low and unstable CMP removal rates (CMP RR). This is particularly problematic with embedded memory applications. For example, large amounts of low-k dielectrics need to be removed due to the resulting step height or surface topography of such applications. This results in long processing times. Furthermore, the long processing time with unstable removal rates results in surface non-uniformity, negatively impacting reliability.
The present disclosure relates to low-k dielectric applications which results in higher and more uniform CMP RR.